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d a t a sh eet product speci?cation file under integrated circuits, ic17 2001 nov 21 integrated circuits PCF5079 dual-band power amplifier controller for gsm, pcn and dcs
2001 nov 21 2 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 contents 1 features 2 applications 3 general description 4 quick reference data 5 block diagram 6 pinning 6.1 pin description 6.2 pin configurations 7 functional description 7.1 general 7.2 power-up mode 7.3 op4 (integrator) 7.4 start-up and initial conditions 7.5 home position voltage 7.6 end of burst 7.7 considerations for ramp-down 7.8 configurations 7.9 summary of current and voltage definitions 7.10 timing 8 limiting values 9 electrostatic discharge (esd) 10 dc characteristics 11 operating characteristics 12 application information 12.1 ramp control 12.2 pa protection against mismatch 12.3 detected voltage measurement 12.4 application examples 13 package outlines 14 soldering (tssop10) 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 soldering (hvson10) 15.1 soldering information 15.2 pcb design guidelines 15.2.1 perimeter pad design 15.2.2 thermal pad and via design 15.2.3 stencil design for perimeter pads 15.2.4 stencil design for thermal pads 15.2.5 stencil thickness 16 data sheet status 17 definitions 18 disclaimers
2001 nov 21 3 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 1 features compatible with baseband interface family pcf5073x two power sensor inputs temperature compensation of sensor signal active filter for digital-to-analog converter (dac) input power amplifier (pa) protection against mismatching bias current source for detector diodes generation of pre-bias level for pa at start of burst (home position) compatible with a wide range of silicon pas compatible with multislot class 12 dual output with internal switch two different transfer functions possibility to adapt dynamic transfer functions very small outline package (3 3 mm). 2 applications global system for mobile communication (gsm) personal communications network (pcn) systems. 3 general description this cmos device integrates an amplifier for the detected rf voltage from the sensor, an integrator and an active filter to build a pa control loop for cellular systems with a small number of passive components. 4 quick reference data ordering information symbol parameter min. typ. max. unit v dd supply voltage 2.5 3.6 5.0 v i dd(tot) total supply current -- 10 ma t amb ambient temperature - 40 - +85 c type number package name description version PCF5079t/c/1 tssop10 plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 PCF5079hk/c/1 hvson10 plastic, heatsink very thin small outline package; no leads; 10 terminals; body 3 3 0.90 mm sot650-1
2001 nov 21 4 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 5 block diagram handbook, full pagewidth rf out rf in d2 pa 30 m a v dd pu filter vdac v dd 30 m a v dd i bias2 i bias1 pu/pd commands PCF5079 control logic phases rf out rf in d1 pa mgt325 10 m a v dd v ss v ss v dd 10 m a op1 op4 d 7 4 523 c1 c4 s1 cint1 cint2 6 pf 10 pf c2 6 pf c3 g = 0.3 16.6 pf v dd v prebias v home 10 v ss 6 8 9 pu bs sf g sf d s5 20 k w r1 6 k w r4 op4 g op4 in op4 vdac vs2 vs1 vcd 1 vcg band gap and current reference vint(n) auxdac3 pcf5073x s3 s4 pu op4 pu d pu g pu ref pu op1 fig.1 block diagram.
2001 nov 21 5 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 6 pinning 6.1 pin description note 1. o = output, i = input, i/o = input/output, a = analog, d = digital, p = power supply and g = ground symbol pin type (1) description vcg 1 o and a pa control voltage output (gsm) vint(n) 2 i and a negative integrator input vcd 3 o and a pa control voltage (dcs) vs1 4 i/o and a sensor signal input 1 vs2 5 i/o and a sensor signal input 2 v ss 6 g reference ground vdac 7 i and a dac input voltage pu 8 i and d power-up input bs 9 i and d band selection input v dd 10 p positive supply voltage 6.2 pin con?gurations handbook, halfpage mgt326 PCF5079t 1 2 3 4 5 10 9 8 7 6 vcg vint(n) vcd vs1 vs2 v ss vdac pu bs v dd fig.2 pin configuration (top view) for PCF5079t, pins are numbered counter-clockwise. handbook, halfpage v dd v ss vdac pu bs vs2 5 4 3 2 1 6 7 8 9 10 vs1 vcd vint(n) vcg PCF5079hk mgu268 fig.3 pin configuration (bottom view) for PCF5079hk, pins are numbered clockwise.
2001 nov 21 6 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 7 functional description 7.1 general the PCF5079 contains an integrated amplifier for the detected rf voltage from the sensor, an integrator and an active filter to build up a pa control loop for cellular systems with a small number of passive components suitable for dual-band applications. the active band can be selected by means of the dedicated input bs. the sensor amplifier can amplify signals from an rf power detector in a range of less than - 20 to +15 dbm. this can comply to the pa output power range of gsm900/1800/1900 systems when, for example, a directional coupler with 20 db attenuation is used for gsm900 and a directional coupler with 18 db attenuation is used for gsm1800. the external schottky diodes for power detection (sensor) are biased by an integrated current source of 30 m a. variations of the forward voltage with temperature have no influence on the measured signal because they are cancelled by the switched capacitor amplifier op1. an external dac with at least 10-bit resolution (for example, auxdac3 of baseband interface family pcf5073x) is necessary to control the loop. an integrated active filter smooths the voltage steps of the dac during ramp-up and ramp-down. the operation principle is the same, independently of the selected standard. the dac signal and the sensor signal are added by amplifier op1. the voltage difference of both signals is integrated by operational amplifier op4 dedicated to the selected standard, which delivers the pa control voltage on an external capacitance, cint1 or or cint2, between pins vint(n) and vcd or vcg, respectively. the shape of the rising and falling power burst edges can be determined by means of the dac voltage. 7.2 power-up mode the device includes a power-up input (pin pu) to switch the ic on during time slots that are used in tdma systems, and to switch the ic off during the unused slots to reduce current consumption. 7.3 op4 (integrator) the operational amplifier op4 (integrator) consists of a shared input stage, op4 in and a dedicated output driver for each standard, op4 g and op4 d . depending on the status of input bs, one driver is active and the other is kept in power-down mode during active time slots. 7.4 start-up and initial conditions the PCF5079 is designed to operate in bursts, as required in tdma systems. referring to fig.4, for each time slot to be transmitted the PCF5079 must be enabled by setting signal pu to logic 1. once pin pu is active, bs is taken into account to allow correct initialisation of switches s1, sf d ,sf g , s3, s4 and s5, and of the configuration signals pu g and pu d . the feedback switch across the unused driver is kept open and the output voltage from the unused driver is tied to v ss to maintain the off state of the unused pa. when pin pu is set to logic 1, at least 5 m s after v dd has reached its final value, switches s1, the appropriate switch sf d or sf g and s3 are closed, and switches s4 and s5 are opened. because switch s1 is closed, the forward voltage of schottky diodes d1 and d2 is sampled on capacitors c1 and c2 respectively. moreover, the control voltage on pin vcd or vcg is initially forced to be at the pre-bias voltage because the appropriate switch sf d or sf g and s3 are closed, and s4 is opened. after a fixed time, defined on-chip, switch s1 is opened and the circuit is ready. once switch s1 is open, a ramp signal applied at pin vdac (at least 20 m s after the transition of pin pu from logic 0 to logic 1) with an amplitude of at least 70 mv, from code start to code kick , determines the opening of switch s3 and closing of switch s4 on the home voltage, with a delay of 3 m s maximum with respect to the ramp. after switch s3 opens (in a fixed amount of time), the control voltage on pin vcd or pin vcg rises to the home position to bias the pa to the beginning of the active range of its control curve. during this time (typically 2 m s), the appropriate switch sf d or sf g remains closed. when the appropriate switch sf d or sf g is opened, switch s5 is closed, allowing the transfer of any signal coming from amplifier op1. after this preset, the control voltage is free to increase according to the control loop if the rf input is enabled (see fig.12). for higher dac ramp steps, the delay of switch s3 opening (s4 closing) is reduced while the delay between switch sf d (sf g ) opening with respect to s3 opening (s4 closing) remains unchanged.
2001 nov 21 7 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 handbook, full pagewidth 46 2 0 8 . . . time time time time closed open closed open closed open closed open closed open time time time (qb) time time mgt327 v prebias v vcd, v vcg v home code start code kick v vdac t d1 t d2 t d3 t d4 v dd pu s5 sf d , sf g s4 s3 s1 > 70 mv > 20 m s < 3 m s (max) 2 m s (typ) > 5 m s fig.4 start-up and initialization timing diagram. the maximum value of code start is limited by the isolation requirement of the pa used in the application. the pulse determined by code kick minus code start applied for two quarter-bits ensures a start-up of the control voltage with very low jitter and high repetitivity. the codes following code kick have to be chosen to get the best ramp shape and spectrum performance.
2001 nov 21 8 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 7.5 home position voltage internally, a forward voltage of an on-chip silicon diode is provided as a default home position. this voltage matches the requirements at the control input of most pas and exhibits the same temperature coefficient. 7.6 end of burst the ramp-down should drive the pa from conduction to shut off in a controlled way (see fig.5). to get this result, correct dac programming is required, so that the last code of the dac ramp-down (code end ) is lower than the initial code of the ramp-up (code start ). in this way, the energy corresponding to the difference between start and end codes, applied for a certain number of quarter-bits (qb), is used to balance the energy stored in the summing node during the time interval between the start of control voltage on pin vcd or vcg ramping-up and the feedback of a detected ramp to the sensor input. also a very slow ramp-down is avoided when the pa switches off and the loop gain becomes zero. the amount of energy required at the end of the ramp-down depends on the overall loop gain and on the time needed to reach pa conduction from the home position. at the end of a burst, when pin pu is set to logic 0, control voltage on pin vcd or vcg is forced to v ss . handbook, full pagewidth v ss v vcd, v vcg time time (qb) time open closed open closed time time code start code end v vdac pu s1, s3 s4, s5 mgt328 t a (1) t d5 < 1 m s . . . i - 8i - 6i - 4i - 2i fig.5 end of burst timing diagram. (1) the exact duration of t a depends on both PCF5079 and the application loop characteristics. the contribution of PCF5079 is due mainly to the group delay of the low-pass filter on the vdac input (see fig.11).
2001 nov 21 9 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 7.7 considerations for ramp-down referring to fig.5, the i-th code can be programmed to have either the code end or code start value or any code between, depending on the application preferences. these codes do not produce any power at the output of the pa, as code start has been chosen to keep the pa isolation. the proper conclusion of the ramp-down is ensured by choosing code end < code start so that the discharge of the integration capacitance is controlled until the control voltage on pin vcd or vcg goes below the pa conduction threshold and by applying at this time the pu transition from logic 1 to logic 0. at the beginning of a burst, the vdac signal steps applied at op1 are not compensated by any signal at the sensor input up to when pin vcd or vcg voltage is greater than the pa conduction threshold voltage. in any case, the initial dac voltage steps are stored in the capacitance of amplifier op1. code end has to be chosen so that the energy inside the shaded zone cancels the energy accumulated in the summing node (op1) at the start of a burst and not balanced by a feedback signal at the sensor input. the exact value of the energy required depends on the specific pa, on the characteristics of the overall loop and on the values chosen for the settable parameters inside the loop. a rough idea can be derived with a simplified analysis of a ramp-up, ramp-down cycle using the following simplifications: the starting conditions for op1 and op4 are biasing at v home with zero charge on capacitances the initial rising of pin vcd or vcg voltage from v home is caused only by the integration of the constant code kick vdac is treated as applied directly at the summing node, initially neglecting the transmission delay through the internal low-pass filter. generally, the integrator op4 input can be expressed as (1) where g s and g d are respectively the gains of sensor input and dac input in the summing amplifier op1. equation (1) holds for closed loop operation. in the time interval between the rising of pin vcd or vcg voltage due to code kick (t = 0) and when v conduction for the pa is reached (t = t 1 ), d v s is 0 and operation is open loop. in this time interval, a charge accumulates in the summing node, which remains uncompensated. time t 1 can be calculated with the preceding simplification. now, to define the quantity (2) the current/voltage equations around the integrator op4 can be solved by forcing the current through r1 to be equal to the current through the integration capacitance and calculating the d v generated on c int , then (3) where (4) substituting equation (4) into equation (3) (5) under the hypothesis the voltage is constant: (6) equation (6) can be used to calculate time t 1 at which the conduction of the pa is reached, considering that (7) (8) time t 1 depends on the time constant of the integrator, by the pa and by d v kick . the condition to be fulfilled is that the energy contained in the shaded zone (fig.5) is at least equal to the energy accumulated at the beginning: (9) where k is the number of quarter-bits during which code end is applied. v in integrator () g s d v s g d d v vdac C = d v kick code kick code start C = d v cint 1 c cint -------------- - i t ()t d 0 t = i t () g d d v kick r1 ------------------------------ - = d v cint 1 c cint r1 ---------------------------- - g 0 t d d v kick d t = d v cint 1 c cint r1 ---------------------------- - g d d v kick t = tt 1 v home d v cint v conduction = + t = t 1 r1 c cint v conduction v home C g d d v kick ----------------------------------------------- = v out op1 2 (t) dt = k qb code end code start C () 2 0 t 1
2001 nov 21 10 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 7.8 con?gurations table 1 operating conditions table 2 band selection con?guration note 1. bs input has to be set before the pu transition logic 0 to logic 1. 7.9 summary of current and voltage de?nitions refer to figs 1, 4 and 12. 7.10 timing refer to figs 4 and 5. power-up input (pu) operating mode 0 disabled; reset 1 enabled band select input (bs) (1) band driver switches control voltage 0 gsm op4g ? active; op4d ? power-down sf g ? working; sf d ? open v vcg ? working; v vcd ? v ss 1 dcs op4d ? active; op4g ? power-down sf d ? working; sf g ? open v vcd ? working; v vcg ? v ss symbol description v vs1 sensor signal of incident rf power or power sensor 1 signal v vs2 sensor signal of re?ected rf wave or power sensor 2 signal v vdac dac voltage v vcg control voltage of pa v vcd control voltage of pa v home home position voltage v prebias prebias reference voltage; used at the start-up i bias1 bias current for detector diode d1 i bias2 bias current for detector diode d2 rf in input signal to the power ampli?er rf out output signal from the power ampli?er symbol definition min. max. unit t d1 delay time; v dd application to pu input transition logic 0 to 1 5.0 -m s t d2 delay time; pu input transition logic 0 to 1 to v vdac ramp-up 20 -m s t d3 v vdac ramp-up detection time - 3.0 m s t d4 delay time; ramp-up detected to v vcd , v vcg =v home - 2.6 m s t d5 delay time; pu input transition logic 1 to 0 to end of burst - 1.0 m s
2001 nov 21 11 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 8 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. where and the thermal resistance between junction and ambient r th(j-a) = 206.3 k/w. 2. where r th(j-a) = 77 k/w on jedec 2s2p board (100 100 mm). 3. human body model: c = 100 pf; r = 1.5 k w. 4. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 9 electrostatic discharge (esd) the PCF5079 is compliant to the general quality specification for integrated circuits snw-fq-611d under the stress condition edsh (human body) and the stress condition esdm (machine model). 10 dc characteristics v dd = 2.5 to 5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage 2.5 +6.0 v v i dc input voltage on all pins except vs1 and vs2 - 0.5 v dd + 0.5 v v vs1 , v vs2 dc input voltage on pins vs1 and vs2 - 3.0 v dd + 0.5 v i i dc current into any signal pin - 10 +10 ma p tot total power dissipation tssop10 package - 315 (1) mw hvson10 package - 844 (2) mw v es electrostatic handling voltage human body model; note 3 2000 - v machine model; note 4 pins 4 and 5 150 - v all other pins 200 - v t stg storage temperature - 65 +150 c t amb ambient temperature - 40 +85 c symbol parameter condition min. typ. max. unit supply v dd supply voltage 2.5 3.6 5.0 v i dd(op) total operating current no load on pins vcd or vcg -- 10 ma i dd(idle) total idle current no load on pins vcd or vcg; note 1 -- 10 m a logic inputs (pins pu and bs) v il low-level input voltage 0 - 0.3 v v ih high-level input voltage v dd = 2.5 to 3.7 v 0.9 - v dd v v dd = 3.7 to 5.0 v 0.95 - v dd v i ll low-level input leakage current v il =0v - 5 - +5 m a p tot t j t amb C r th(j-a) ----------------------- =
2001 nov 21 12 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 note 1. a resistive load on pins vcd or vcg to ground (v ss ) does not result in additional current consumption. i lh high-level input leakage current v ih = 5.0 v - 5 - +5 m a c i input capacitance - 10 - pf sensor inputs and bias current source (pins vs1 and vs2) v vs2 input voltage - 3 - v dd v v vs1 input voltage - 3 - v dd v i bias1 , i bias2 bias current source for detector diodes d1 and d2 v i =0v; t amb =25 c; see fig.6 v dd =2.5v 172839 m a v dd =5.0v 213345 m a tc ibias1 , tc ibias2 temperature coef?cient of i bias1 and i bias2 - 0.07 - ma/k internal home position voltage v home internal home position voltage t amb =25 c 0.550 0.600 0.650 v tc vhome temperature coef?cient for v home -- 2.1 - mv/k symbol parameter condition min. typ. max. unit handbook, halfpage 2.5 3.5 4.5 345 v dd (v) i bias ( m a) 35 27 mgt332 33 31 29 fig.6 typical value of i bias as a function of v dd at t amb =25 c.
2001 nov 21 13 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 11 operating characteristics v dd = 2.5 to 5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. guaranteed by design. 2. slew rates are measured between 10% and 90% of output voltage interval with a load of 40 pf to ground. symbol parameter condition min. typ. max. unit integrator (op4g and op4d) v dd supply voltage 2.5 3.6 5.0 v b g gain bandwidth c l = 120 pf; note 1 - 4 - mhz psrr power supply ripple rejection f = 217 hz; v dd = 3 v; note 1 50 55 - db sr pos positive slew rate v dd = 3 v; note 2 2.0 3.2 - v/ m s sr neg negative slew rate v dd = 3 v; note 2 2.0 3.2 - v/ m s v o(min) minimum output voltage t amb = 25 c; see fig.7 -- 0.2 v v o(max) maximum output voltage r l = 350 w ; see fig.8 0.85v dd -- v capacitors c1, c2 and c4 m matching ratio accuracy between c1, c2 and c4 - 1 - % low-pass ?lter for dac signal (3rd-order bessel ?lter) f 3db corner frequency 70 100 130 khz t d(group) group delay time see fig.11 1.8 3.0 4.2 m s handbook, halfpage 2.5 3.5 4.5 345 v dd (v) mgt333 0.258 0.250 0.256 0.254 0.252 tc (mv/k) fig.7 temperature coefficient of v o(min) as a function of v dd . handbook, halfpage 2.5 3.5 4.5 345 v dd (v) i l (ma) 13 5 mgt334 11 9 7 fig.8 minimum load current as a function of v dd .
2001 nov 21 14 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 handbook, halfpage 300 1300 r l ( w ) 1 v vcd or v vcg v dd 0.80 0.84 mgt335 0.88 0.92 0.96 500 700 900 1100 fig.9 minimum as a function of r l . v vcd or v vcg v dd ------------------------------------ v dd = 2.5 v. handbook, halfpage 2.5 3.5 4.5 345 v dd (v) 1 0.6 mgt336 0.9 0.8 0.7 (1) (2) (3) v vcd or v vcg v dd fig.10 minimum as a function of v dd . v vcd or v vcg v dd ------------------------------------ (1) i l = 6 ma. (2) i l = 8 ma. (3) i l =10ma. handbook, halfpage 4 0 2 3 1 mgw101 10 3 10 4 10 5 f (hz) delay ( m s) 10 6 fig.11 low-pass filter group delay at pins vcd and vcg (typical values).
2001 nov 21 15 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 12 application information handbook, full pagewidth v prebias - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 rf out (dbc) - 28 - 18 - 10 0 + 543 + 553 + 561 + 571 time ( m s) typ < 0.9v dd of pcf5073x typ > 0.85v dd with r l = 350 w pa conduction threshold code start code start (1) code end code kick v vdac v vcd, v vcg pu (PCF5079) rf in mgt329 time time t a (2) 0246810121416 16 + n 18 + n 20 + n 22 + n 24 + n 26 + n 28 + n 30 + n 32 + n nx (2 qb) time (2 qb) 0246810121416 16 + n 18 + n 20 + n 22 + n 24 + n 26 + n 28 + n 30 + n 32 + n nx (2 qb) time (2 qb) > 20 m s < 1 m s apedac3 (pcf5073x) time fig.12 timing diagram for one time slot with pcf5073x family. (1) the software design must guarantee that code start is applied before the pu transition from logic 0 to logic 1. (2) the exact duration of t a depends on both PCF5079 and the application loop characteristics. the duration should be long enough to ensure that v vcd ,v vcg is below the pa conduction threshold. the contribution of PCF5079 is mainly due to the group delay of the low-pass filter on the vdac input (see fig.11).
2001 nov 21 16 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 handbook, full pagewidth r2 1 k w r1 1 k w mgt337 PCF5079 1 2 3 4 5 10 9 8 7 6 vcg cint1 < 50 pf cint2 < 50 pf rf section auxdac3 pcf5073x vint(n) vcd vs1 vs2 v ss vdac 0 to 2.3 v pu bs v dd fig.13 diagram showing external components required. 12.1 ramp control code kick and v home define the starting conditions for ramping-up. ramping-up and ramping-down are defined by v vdac . code end and code start define the correct shut-off of the power module. the non-linear behaviour of the control curves of the power modules has a large influence on the loop. starting conditions in the flat area of the control curve are critical and need some attention. initially the voltage on pins vcd (vcg) will be at the home position. successively, the integrator is moved into the active part of the control curve. this is achieved by integrating code kick . when vcd (vcg) voltage has reached the active region of the control curve, the loop is closed and the circuit can follow the ramping function generated at pin vdac. the top value of vdac voltage determines the power of the transmit burst. ramping-down is started according to the decrease of vdac voltage. the loop follows the leading function for ramping-down until the rf sensor leaves its active region. the reason for code start and code end is to shorten the tail of the slope. mgt338 handbook, halfpage r l v vcd, v vcg i l 350 w 120 pf fig.14 worst case load on control voltage pins vcg and vcd.
2001 nov 21 17 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 12.2 pa protection against mismatch high vswr at the pa output may occur in systems where the pa is connected to the antenna via couplers and switches with low insertion loss, depending on the antenna matching. the incident and reflected power have to be monitored and care has to be taken to prevent the summed rf power does not exceed the defined maximum value at the pa output. as two sensor inputs are available in the PCF5079, two different detector signals can be combined: one for direct path and one for reflected path. these two voltages, fed to the sensor inputs, are summed inside the PCF5079 resulting in a decrease in the pa output power if there is an increase of the vswr at the antenna port (see fig.15). handbook, full pagewidth mgt330 pa band select switch d1 d2 c1 vs1 c2 vs2 r2 r1 rf in hb rf out rf in lb broad band coupler fig.15 example of pa mismatch protection circuit. table 3 table of components (see fig.15) symbol component description d1, d2 detector diode philips 1ps79sb62 r1, r2 resistor r = 1 k w (decoupling versions) c1, c2 capacitor c = 39 pf - band select switch motorola; alpha industries; m/a; com gaas mmic; or discrete pin diode, e.g. philips bap51-03 - broad band coupler murata lcd20 series; tdk hhm 20, 22 series
2001 nov 21 18 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 12.3 detected voltage measurement rf gmsk modulated signal mgu223 gsm: 39 pf dcs: 8.2 pf 1 k w v dd PCF5079 probe fig.16 set-up for measuring detected voltage for 900 mhz and 1800 mhz working. handbook, full pagewidth - 20 - 15 - 10 - 5 5 10 15 p in (dbm) v vs1, v vs2 0 (2) (1) 10 1 10 - 1 10 - 2 mgu224 fig.17 detected voltage as a function of incident power for 1ps79sb62 detector diodes. (1) dcs. (2) gsm.
2001 nov 21 19 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 12.4 application examples handbook, full pagewidth bs pa module rf in rf in rf out v apc rf out r2 d1 d2 r1 gsm1800 gsm900 mgt331 PCF5079 1 2 3 4 5 10 9 8 7 6 vcg cint1 auxdac3 pcf5073x vint(n) vcd vcd vs1 vs2 v ss vdac 0 to 2.3 v pu bs v dd fig.18 application example of a dual-band pa module with single control input.
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 nov 21 20 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 handbook, full pagewidth mgt757 39 pf high gain uhf amplifier module 47 pf 47 pf 53 2 PCF5079 bgy280 14 10 6 9 v c2 v c1 vcd vcg vs1 vs2 v s1 txgsm txdcs v s2 v ss v dd vint(n) 8 7 bs pu vdac band select power-up control voltage + 2.4 to 6 v + 3.6 v 47 w 1 k w 1ps79sb62 220 m f 100 nf 100 nf murata ldc15h200j0897 rf out gsm rf ingsm rf indcs 8 9 10 11 14 4 12 1 2 3 6 16 15 13 57 8.2 pf 47 w 47 w (1) 68 w (1) 1 k w 1ps79sb62 murata ldc15h180j1747 rf out dcs fig.19 application diagram. (1) precise value depends on the pcb design.
2001 nov 21 21 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 13 package outlines unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.15 0.23 0.15 3.10 2.90 3.10 2.90 0.50 5.00 4.80 0.67 0.34 6 0 0.1 0.1 0.1 0.95 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.70 0.40 sot552-1 99-07-29 w m b p d z e 0.25 15 10 6 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop10: plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 1.10 pin 1 index
2001 nov 21 22 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 0.5 0.90 0.85 0.60 a 4 e h b unit d y e references outline version european projection issue date iec jedec eiaj mm 3.20 2.80 d h 1.75 1.45 y 1 3.20 2.80 2.55 2.25 0.30 0.18 0.05 0.1 dimensions (mm are the original dimensions) sot650-1 mo-229 e 0.50 0.30 l 0.2 v 0.1 w 0 2 mm 1 scale sot650-1 hvson10: plastic, heatsink very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.90 mm a max. a a 4 detail x y y 1 c d h e h bottom view e l b 10 5 1 6 x d e c b a w m m vb 01-01-22 terminal 1 index area
2001 nov 21 23 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 14 soldering (tssop10) 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 nov 21 24 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 nov 21 25 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 15 soldering (hvson10) 15.1 soldering information information contained within this chapter is of a preliminary nature and may change without notice. 15.2 pcb design guidelines these guidelines are to help the user in developing the proper pcb design. for the surface mount process refer to data handbook ic26; integrated circuit packages (document order number 9398 652 90011). 15.2.1 p erimeter pad design referring to fig.20, dimensions z and g are respectively the outside to outside and the inside to inside pad dimensions. the dimensions x and y indicate respectively the width and the length of the pad. note that the calculated x dimension is the maximum value in order to avoid solder bridging between adjacent pads.the calculated y dimension is the minimum value and therefore pad design should start with this value and the pad length at the outside be extended if more solder joint fillets are required. the dimension cpl defines the minimum distance between the inner tip of the pad and the outer edge of the thermal pad. it is suggested that this dimension be fixed at 0.15 mm to avoid solder bridging issues between the thermal pad and the perimeter pads. handbook, full pagewidth mgw498 cpl = 0.15 0.33 0.30 thermal via z = 3.46 3.27 y = 0.69 0.55 g = 2.09 1.20 1.00 x = 0.28 0.50 typ 2.00 ref 1.20 1.00 fig.20 hvson10 pcb pattern. dimensions in mm. the solder mask opening dimension should be larger than the pad dimension by 125 to 150 m m. 15.2.2 t hermal pad and via design the size of the thermal pad should at least match the size of the exposed die-attach paddle. however, in some cases, the die-attach paddle size may need to be modified to avoid solder bridging between the thermal pad and the perimeter pads. in order to effectively transfer heat from the top metal layer to the inner or bottom layers of the pcb, thermal vias should be incorporated into the thermal pad design. the number of thermal vias will depend on the application and on the power dissipation and electrical requirements. it is recommended to incorporate an array of thermal vias at a pitch of 1.0 to 1.2 mm with the via diameter between 0.3 and 0.33 mm.
2001 nov 21 26 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 15.2.3 s tencil design for perimeter pads for optimum paste release the area and aspect ratios of the stencil should be greater than 0.66 and 1.5 respectively. where: l = aperture length w = aperture width t = stencil thickness. 15.2.4 s tencil design for thermal pads in order to remove the heat effectively from the package and to enhance electrical performance the die-attach paddle needs to be soldered to the pcb thermal pad, preferably with minimum voids. it is therefore recommended that smaller, multiple openings in a stencil should be used instead of one large opening for printing solder paste in the thermal pad region. this results typically in 50% to 80% solder paste coverage. two examples are shown in fig.21. 15.2.5 s tencil thickness a stencil thickness of 0.125 to 0.150 mm is recommended but this value needs to be optimized by the user to find the proper thickness according to application requirements. area ratio area of aperture opening aperture wall area ----------------------------------------------------------------- lw 2t(l + w) -------------------------- = = aspect ratio aperture width stencil thickness ------------------------------------------- w t ----- == handbook, full pagewidth mgw499 fig.21 examples of thermal pad stencil design. a. outline of 0.4 mm 2 2 2 array giving 44% solder paste coverage. b. outline of 1.2 mm 2 2 1 array giving 60% solder paste coverage.
2001 nov 21 27 philips semiconductors product speci?cation dual-band power ampli?er controller for gsm, pcn and dcs PCF5079 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403506/01/pp 28 date of release: 2001 nov 21 document order number: 9397 750 07095

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